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Align DeepSeek and GLM execution with DS4

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This commit is contained in:
Georg Bauer
2026-09-11 17:18:45 +02:00
parent 02db0968ae
commit 48c2f751b4
27 changed files with 4517 additions and 400 deletions
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native/metal/ds4_metal.m
-42
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@@ -1201,48 +1201,6 @@ static void ds4_gpu_busy_stats_record(id<MTLCommandBuffer> cb, uint64_t epoch) {
}
}
/* A separate queue used by the headless evaluator's supervisor process. The
* tiny blit measures whether another process can still schedule UI-sized GPU
* work while the model owns its own Metal queue. */
static id<MTLDevice> g_canary_device;
static id<MTLCommandQueue> g_canary_queue;
static id<MTLBuffer> g_canary_buffer;
static double ds4_monotonic_seconds(void) {
struct timespec time;
if (clock_gettime(CLOCK_MONOTONIC, &time) != 0) return 0.0;
return (double)time.tv_sec + (double)time.tv_nsec / 1000000000.0;
}
int ds4_gpu_canary_probe(ds4_gpu_canary_sample *sample) {
if (!sample) return 0;
sample->scheduled_seconds = 0.0;
sample->completed_seconds = 0.0;
@autoreleasepool {
if (!g_canary_device) g_canary_device = MTLCreateSystemDefaultDevice();
if (!g_canary_queue && g_canary_device) {
g_canary_queue = [g_canary_device newCommandQueue];
}
if (!g_canary_buffer && g_canary_device) {
g_canary_buffer = [g_canary_device newBufferWithLength:4096
options:MTLResourceStorageModeShared];
}
if (!g_canary_queue || !g_canary_buffer) return 0;
id<MTLCommandBuffer> cb = [g_canary_queue commandBuffer];
id<MTLBlitCommandEncoder> blit = [cb blitCommandEncoder];
if (!cb || !blit) return 0;
[blit fillBuffer:g_canary_buffer range:NSMakeRange(0, 4096) value:0];
[blit endEncoding];
const double started = ds4_monotonic_seconds();
ds4_gpu_commit_command_buffer(cb);
[cb waitUntilScheduled];
sample->scheduled_seconds = ds4_monotonic_seconds() - started;
[cb waitUntilCompleted];
sample->completed_seconds = ds4_monotonic_seconds() - started;
return cb.status == MTLCommandBufferStatusCompleted;
}
}
/* A failed command buffer can leave a cross-threadgroup arrival counter at an
* arbitrary partial value. Drop cached ownership instead of CPU-resetting